Omer Khan
Professor
Electrical and Computer Engineering
College of Engineering
University of Connecticut
Biography
Dr. Khan is a Professor of Electrical and Computer Engineering at the University of Connecticut. He leads the Computer Architecture Group (CAG) and also serves as an Associate Director of the Connecticut Advanced Computing Center (CACC). His research interests include computer architectures that exploit parallelism and locality for high-performance applications, such as graph intelligence problems. He has contributed architectural advancements for futuristic massively parallel microprocessors that substantially enhance system level performance and efficiency. Prior to joining UConn, Khan was a Postdoctoral Research Scientist at the Massachusetts Institute of Technology. He received Ph.D. from the University of Massachusetts Amherst. He spent several years in the semiconductor industry as a high-performance processor architect.
Dr. Khan is addressing the computational complexity problem in artificial intelligence applications, such as autonomous systems, social influence, and chip design that must handle increasingly large and sparse graph-based data. Efficient processing of sparse graph problems is extremely challenging since the underlying computations require complex mathematical operations whose processing suffers from performance scaling challenges on existing hardware processing units. He is developing parallel architectures that exploit sparsity for performance to reduce computational complexity in graph intelligence problems.
As a complementary research effort, Dr. Khan is developing a system architecture that takes a hardware-architecture-algorithm approach to optimize multiple goals at once, like finding the best trade-off between speed and fuel efficiency for autonomous vehicles. His approach exploits massive parallelism and architectural enhancements to rapidly accelerate the computationally hard multi-objective graph intelligence problems. This means exact solutions that used to take hours to generate can be found in seconds or less. This allows decision-makers to have access to real-time information, leading to better decision-making in high-impact application scenarios.
Announcements
Recruiting PhD students to work on massively parallel computer architectures for graph intelligence problems. Contact me via email.
Interests
- Computer Architecture
- Parallel Processor
- Secure Processor
- Graph Intelligence
Education
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PhD in Electrical and Computer Engineering, 2009
University of Massachusetts Amherst
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BSc in Electrical and Computer Engineering, 2000
Michigan State University
