Welcome to ECE 3401 - Digital Systems Design

Course Syllabus

Instructor

• Omer Khan
• Office: ITEB 447
• Email: khan@uconn.edu
• Office Hours: same as TA hours or by appointment via email

TAs

• Hanan Khan
• Email: abdul_hanan_gul.khan@uconn.edu
• Mondays and Wedbesdays 9-10am in ITE 430

Announcements

Lectures

• Lecture 1: Introduction to Logic Design and Hardware Descriptive Languages - PDF (textbook reading: 1.1 - 1.5)
• Lecture 2: Combinatorial Logic and VHDL - PDF (textbook reading: 2.1 - 2.4) (VHDL example: cir1.vhd, cir1test.vhd, Makefile)
• Lecture 3: VHDL Modules, Types, Operators, Libraries - PDF (textbook reading: 2.4, 2.12.1, 2.10.1) (VHDL examples: cir3_1.vhd, bit_adder.vhd, cir3_1test.vhd cir3_2.vhd, cir3_2test.vhd, Makefile)
• Lecture 4: VHDL Operators, Libraries, and Introduction to Sequential Logic - PDF (textbook reading: 2.10.2, 2.13, 1.6) (VHDL examples: cir4_1.vhd, cir4_1test.vhd cir4_2.vhd, cir4_2test.vhd, cir4_3.vhd, cir4_3test.vhd, Makefile)
• Lecture 5: Sequential Logic Modeling and VHDL - PDF (textbook reading: 1.6, 2.5, 2.6, 2.7, 2.12.2, 2.9) (VHDL examples: cir5_1.vhd, cir5_1test.vhd, Makefile)

Homeworks (due at HuskyCT specified deadline - no late submissions will be accepted)

• Homework 1: PDF (VHDL: q4.vhd, tb_q4.vhd, Makefile) (due via HuskyCT on Feb 3, 2025 11:59pm EST)

Programming Assignments (due at HuskyCT specified deadline - no late submissions will be accepted)

• VHDL Toolchain guide to setup the required open-source software PDF (no due date, but complete at the earliest!)
• PA 0 (due via HuskyCT on Jan 27, 2025): Complete all steps for the toolchain setup and run the lab0 with test0 testbench. Upload a single PDF of your submission in HuskyCT. PA0 PDF, lab0.vhd, test0.vhd, Makefile
• PA 1 (due via HuskyCT on Feb 17, 2025): Datapath Logic for LCM and GCD Digital Design PA1-Handout PDF, pa1s25.zip