Welcome to ECE 3401 - Digital Systems Design

Electrical and Computer Engineering
University of Connecticut

Spring 2025

Tuesdays and Thursdays 12:30pm - 1:45pm, ITE 119

Course Syllabus

Instructor

Omer Khan
Office: ITEB 447
Email: khan@uconn.edu
Office Hours: same as TA hours or by appointment via email

TAs

Hanan Khan
Email: abdul_hanan_gul.khan@uconn.edu
Mondays and Wedbesdays 9-10am in ITE 430

Announcements

Final Exam is scheduled in ITE 119 from 3:30-5:30pm on May 9, 2025 (all lectures)

Exam 2 is scheduled in-person, in-class on April 15, 2025 (lectures 9 through 17 inclusive)

Exam 1 is scheduled in-person, in-class on March 4, 2025 (lectures 1 through 9 inclusive)

Lectures

Lecture 1: Introduction to Logic Design and Hardware Descriptive Languages - PDF (textbook reading: 1.1 - 1.5)

Lecture 2: Combinatorial Logic and VHDL - PDF (textbook reading: 2.1 - 2.4) (VHDL example: cir1.vhd, cir1test.vhd, Makefile)

Lecture 3: VHDL Modules, Types, Operators, Libraries - PDF (textbook reading: 2.4, 2.12.1, 2.10.1) (VHDL examples: cir3_1.vhd, bit_adder.vhd, cir3_1test.vhd cir3_2.vhd, cir3_2test.vhd, Makefile)

Lecture 4: VHDL Operators, Libraries, and Introduction to Sequential Logic - PDF (textbook reading: 2.10.2, 2.13, 1.6) (VHDL examples: cir4_1.vhd, cir4_1test.vhd cir4_2.vhd, cir4_2test.vhd, cir4_3.vhd, cir4_3test.vhd, Makefile)

Lecture 5: Sequential Logic Modeling and VHDL - PDF (textbook reading: 1.6, 2.5, 2.6, 2.7, 2.12.2, 2.9) (VHDL examples: cir5_1.vhd, cir5_1test.vhd, Makefile)

Lecture 6: VHDL Modeling and Simulation - PDF (textbook reading: 2.12.2, 2.8, 2.9)

Lecture 7: VHDL Simulation - PDF (textbook reading: 2.9) (VHDL examples: cir7_1.vhd, cir7_1test.vhd, cir7_2.vhd, cir7_2test.vhd, cir7_3.vhd, cir7_3test.vhd, cir7_4.vhd, cir7_4test.vhd, Makefile)

Lecture 8: VHDL Synthesis - PDF (textbook reading: 2.11, 2.14)

Lecture 9: VHDL Counter, Arrays, Loops - PDF (textbook reading: 2.14, 2.16, 2.17, 2.18, 2.19) (VHDL examples: cir9_1.vhd, cir9_1test.vhd, cir9_2.vhd, cir9_2test.vhd, Makefile)

Lecture 10: Synchronous Finite State Machine Design - PDF (textbook reading: 1.7, 1.8, 2.15.1) (VHDL examples: cir10_1.vhd, cir10_1test.vhd, cir10_2.vhd, cir10_2test.vhd, Makefile)

Midterm 1 Review - Midterm 1 Review PDF

Lecture 11: Synchronous FSM Designs - PDF (textbook reading: 1.7, 1.8, 2.15.1) (VHDL examples: cir11_1.vhd, cir11_1test.vhd, cir11_2.vhd, cir11_2test.vhd, Makefile)

Lecture 12: Synchronous Design Examples - PDF (textbook reading: 4.4, 4.3, 4.8)

Lecture 13: Synchronous Design Examples II - PDF (textbook reading: 4.8)

Lecture 14: State Machine Charts (SM Charts) - PDF (textbook reading: 5.1, 5.3)

Lecture 15: Microprogramming - PDF (textbook reading: 5.5)

Lecture 16: Microprogram Design - PDF (textbook reading: 9.1)

Lecture 17: Processor Design Example - PDF (textbook reading: 9.1)

Lecture 18: Reduced MIPS Processor Implementation - PDF

Midterm 2 Review - Midterm 2 Review PDF

Lecture 19: High-Level Synthesis (HLS) I - PDF (no textbook reading)

Lecture 20: High-Level Synthesis (HLS) II - PDF (no textbook reading)

Homeworks (due at HuskyCT specified deadline - no late submissions will be accepted)

Homework 1: PDF, Solution PDF (VHDL: q4.vhd, tb_q4.vhd, Makefile) (due via HuskyCT on Feb 3, 2025 11:59pm EST)

Homework 2: PDF, Solution PDF (due via HuskyCT on Feb 12, 2025 11:59pm EST)

Homework 3: PDF, Solution PDF (VHDL: tb_q1.vhd) (due via HuskyCT on Feb 25, 2025 11:59pm EST)

Homework 4: PDF, Solution PDF (due via HuskyCT on March 14, 2025 11:59pm EST)

Homework 5: PDF, Solution PDF (due via HuskyCT on April 1, 2025 11:59pm EST)

Homework 6: PDF, Solution PDF (due via HuskyCT on April 11, 2025 11:59pm EST)

Programming Assignments (due at HuskyCT specified deadline - no late submissions will be accepted)

VHDL Toolchain guide to setup the required open-source software PDF (no due date, but complete at the earliest!)

PA 0 (due via HuskyCT on Jan 27, 2025): Complete all steps for the toolchain setup and run the lab0 with test0 testbench. Upload a single PDF of your submission in HuskyCT. PA0 PDF, lab0.vhd, test0.vhd, Makefile

PA 1 (due via HuskyCT on Feb 17, 2025): Datapath Logic for LCM and GCD Digital Design PA1-Handout PDF, pa1s25.zip

PA 2 (due via HuskyCT on Mar 10, 2025): State Machines for LCM and GCD Digital Design PA2-Handout PDF, pa2s25.zip

PA 3 (due via HuskyCT on April 7, 2025): Sparse Matrix Vector Multiplication (SpMV) Design PA3-Handout PDF, pa3s25.zip

PA 4 (due via HuskyCT on April 28, 2025): Sparse Matrix Matrix Multiplication (SpMM) Controller and Datapath Design PA4-Handout PDF, pa4s25.zip